Automatic generation of systemc transactors from graphical FSM

To specify, design, and implement complex system-on-chip (SoC), a new modeling method, transaction level modeling (TLM), has been proposed recently. TLM allows designers to focus on functionality while abstracting implementation details. At the register transfer level (RTL), however, different modules communicate through detailed pin level signaling. SoC design methodologies involve the integration of different intellectual property (IP) blocks modeled at different levels of abstraction. Therefore a special module or channel is needed in order to link modules, IPs, designed at different abstraction levels. This module, called transactor, can be modeled using a finite state machine (FSM) providing a functional specification of the protocol´s behavior. In this paper, we propose a methodology to specify transactors using graphical finite state machine (FSM). This technique enables an automatic generation of SystemC TLM-RTL transactors via an intermediate translation of the user-defined FSM to the Abstract State Machines Language (AsmL). The UTOPIA standard protocol is provided as an illustration of this approach.