Wireplanning in logic synthesis

In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deep submicron technologies. We first show that conventional logic synthesis techniques can produce circuits which will have long paths even if placed optimally. Then, we characterize the conditions under which this can happen and propose logic synthesis techniques which produce circuits which are "better" for placement. Our proposed approach still separates logic synthesis from physical design.