High throughput encoder architecture for DVB-S2 LDPC-IRA codes

Due to their excellent bit-error-rate performance, low density parity check codes (LDPC) have been adopted by the recent digital video satellite broadcast standard (DVB-S2). In order to simplify the encoding procedure, irregular repeat and accumulate (IRA) LDPC codes have been chosen. This paper proposes an efficient, low delay and high throughput encoder architecture shared by all DVB-S2 LDPC-IRA codes. The architecture explores the periodic structure of the adopted codes by performing on the fly partial-parallel computation of the parity check bits. The architecture implementation on a XC2VP30 Virtex2P Xilinx FPGA (@131.7 MHz) shows a minimum throughput of 5.93 Gb/s in worst case conditions. Synthesis results are also presented.