• DocumentCode
    332680
  • Title

    Using a single input to support multiple scan chains

  • Author

    Kuen-Jong Lee ; Jih-Jeen Chen ; Chen-Hua Huang

  • Author_Institution
    Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
  • fYear
    1998
  • fDate
    8-12 Nov. 1998
  • Firstpage
    74
  • Lastpage
    78
  • Abstract
    Single scan chain architectures suffer from long test application time, while multiple scan chain architectures require large pin overhead and are not supported by boundary scan. We present a novel method to allow a single input line to support multiple scan chains. By appropriately connecting the inputs of all circuits under test during ATPG process such that the generated test patterns can be broadcast to all scan chains when actual testing is executed, we show that 177 and 280 test patterns are enough to detect all detectable faults in all 10 ISCAS´85 combinational circuits and 10 largest ISCAS´89 sequential circuits, respectively.
  • Keywords
    automatic test pattern generation; combinational circuits; design for testability; sequential circuits; ATPG process; ISCAS; boundary scan; combinational circuits; detectable faults; generated test patterns; large pin overhead; long test application time; multiple scan chain architectures; multiple scan chains; sequential circuits; single input; single input line; single scan chain architectures; test patterns; Automatic test pattern generation; Broadcasting; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Joining processes; Sequential analysis; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA, USA
  • Print_ISBN
    1-58113-008-2
  • Type

    conf

  • DOI
    10.1109/ICCAD.1998.144247
  • Filename
    742853