Title :
High-level variable selection for partial-scan implementation
Author :
Hsu, F.F. ; Patel, J.H.
Author_Institution :
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
Abstract :
We propose a high level variable selection for partial scan approach to improve the testability of digital systems. The testability of a design is evaluated at the high level based on previously proposed controllability and observability measures. A testability grading technique is utilized to measure the relative testability improvement in a design, as the result of making a subset of the variables fully controllable and observable. The variables that cause the greatest testability improvement are selected and the selection process is performed incrementally until no further testability improvement can be achieved. Then the registers that correspond to the selected variables are placed in the scan chain for partial scan implementation. The experimental results show that the variable selection approach produces partial scan implementations that can achieve high fault coverage, while the logic overheads are fairly low.
Keywords :
CAD; controllability; design for testability; logic testing; observability; controllability; digital system testability; high fault coverage; high level variable selection; logic overheads; observability measures; partial scan approach; partial scan implementation; relative testability improvement; scan chain; selection process; testability grading technique; testability improvement; Algorithm design and analysis; Circuit faults; Circuit synthesis; Circuit testing; Costs; Flip-flops; Input variables; Logic; Permission; Registers;
Conference_Titel :
Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-008-2
DOI :
10.1109/ICCAD.1998.144248