FPGA implementation of a fully digital CDR for plesiochronous clocking systems

This paper describes an FPGA implementation of a fully digital clock and data recovery system (FD-CDR) with plesiochronous clocking. The design utilizes 51 FF´s only. It does require, at worst, 2 preamble bits to get into lock. The extracted clock is not shifted as long as input data jitter is small (typically less than plusmn12.5%UI), thus, minimizing jitter in the extracted clock. Typically, for small input data jitter, the extracted clock shows an rms jitter of 51 ps which is mainly due to the 35.6 ps jitter (rms) of the system lOOMHz-master clock. Besides, it can withstand an input data cycle-to-cycle jitter up to plusmn37.5% UI without getting out of lock. Data are obtained through digital correlation with the incoming symbol instead of ordinary sampling at the middle of the eye pattern, which improves BER. It is insensitive to long runs of transition-free data patterns. Besides, the extracted clock has a 50 % duty cycle.