Title :
Noise considerations in circuit optimization
Author :
Conn, A.R. ; Haring, R.A. ; Visweswariah, C.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability effects. Dynamic logic is particularly susceptible to charge-sharing and coupling noise. Thus, the design and optimization of a circuit should take noise considerations into account. Such considerations are typically stated as semi-infinite constraints. In addition, the number of signals to be checked and the number of sub-intervals of time during which the checking must be performed can potentially be very large. Thus, the practical incorporation of noise constraints during circuit optimization is a hitherto unsolved problem. This paper describes a novel method for incorporating noise considerations during automatic circuit optimization. Semi-infinite constraints representing noise considerations are first converted to ordinary equality constraints involving time integrals, which are readily computed in the context of circuit optimization based on time-domain simulation. Next, the gradients of these integrals are computed by the adjoint method. By using an augmented Lagrangian optimization merit function, the adjoint method is applied to compute all the necessary gradients required for optimization in a single adjoint analysis, no matter how many noise measurements are considered, and irrespective of the dimensionality of the problem. Numerical results are presented.
Keywords :
circuit noise; circuit optimisation; circuit reliability; circuit simulation; digital circuits; electric noise measurement; time-domain analysis; timing; adjoint method; augmented Lagrangian optimization merit function; automatic circuit optimization; charge-coupling noise; charge-sharing noise; circuit design; circuit noise; digital circuits; dimensionality; dynamic logic; equality constraints; gradients; incorrect switching; noise constraints; noise measurements; numerical results; power effects; reliability effects; semi-infinite constraints; signal checking; time integrals; time sub-intervals; time-domain simulation; timing effects; Circuit noise; Circuit optimization; Coupling circuits; Design optimization; Digital circuits; Logic; Optimization methods; Switches; Switching circuits; Timing;
Conference_Titel :
Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-008-2
DOI :
10.1109/ICCAD.1998.144270