Title :
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits
Author :
Ferrandi, F. ; Macii, A. ; Macii, E. ; Poncino, M. ; Scarsi, R. ; Somenzi, F.
Author_Institution :
Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
Abstract :
The paper presents a novel methodology for synthesizing PTL circuits, whose distinctive features are the use of a symbolic algorithm for the covering of the initial network in terms of PTL cells, and the exploitation of layout level area and delay model during the selection of the best covering solution. The results produced by the synthesis procedure on the full suite of the Iscas´85 combinational circuits are very encouraging.
Keywords :
combinational circuits; logic CAD; transistor circuits; ISCAS combinational circuits; PTL cells; PTL circuit synthesis; delay model; layout level area; layout oriented synthesis; pass transistor logic circuits; symbolic algorithm; symbolic algorithms; synthesis procedure; Binary decision diagrams; Capacitance; Circuit synthesis; Cost function; Delay; Inverters; Logic circuits; MOS devices; Network synthesis; Routing;
Conference_Titel :
Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-008-2
DOI :
10.1109/ICCAD.1998.144272
