Test set compaction algorithms for combinational circuits

Author

Hamzaoglu, I. ; Patel, J.H.

Author_Institution

Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA

fYear

1998

fDate

8-12 Nov. 1998

Firstpage

283

Lastpage

289

Abstract

This paper presents two new algorithms, Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under the single stuck at fault model, and a new heuristic for estimating the minimum single stuck at fault test set size. These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combinational circuits, called MinTest. MinTest found better lower bounds and generated smaller test sets than the previously published results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits.

Keywords

VLSI; automatic test pattern generation; circuit analysis computing; combinational circuits; integrated circuit testing; Essential Fault Reduction; ISCAS85 benchmark circuit; ISCAS89 benchmark circuit; MinTest; Redundant Vector Elimination; advanced ATPG system; combinational circuits; dynamic compaction algorithm; heuristic; lower bounds; minimum single stuck at fault test set size estimation; single stuck at fault model; test set compaction algorithms; Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Compaction; Contracts; Costs; Fault detection; Permission;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on

Conference_Location

San Jose, CA, USA

Print_ISBN

1-58113-008-2

Type

conf

DOI

10.1109/ICCAD.1998.144279

Filename

742885