Efficient analog circuit synthesis with simultaneous yield and robustness optimization

The paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The starting point of this methodology is a declarative analytical description of the circuit. An equation manipulation program based on constraint satisfaction converts this declarative model into an efficient design plan for optimization based sizing. The efficiency is due to the use of an operating point driven DC formulation, so that the design plan avoids the calculation of simultaneous sets of nonlinear equations. From the same declarative analytical description also a direct symbolic yield estimation plan is generated. The parametric yield is estimated by propagating the spread of the technological variables through the analytical model towards the performance variables of the circuit. The design plan and the yield estimation plan are then combined together in the inner loop of a global optimization routine. The strength of this methodology lies in the low CPU times needed to perform yield estimation compared to the hours of simulation batches with Monte Carlo simulations, while the accuracy is comparable.