Architecture driven circuit partitioning

Author

Chau-Shen Chen ; TingTing Hwang ; Liu, C.L.

Author_Institution

Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

1998

fDate

8-12 Nov. 1998

Firstpage

408

Lastpage

411

Abstract

We propose an architecture driven partitioning algorithm for netlists with multi terminal nets. Our target architecture is a multi FPGA emulation system with folded Clos network for board routing. Our goal is to minimize the number of FPGA chips used and maximize the routability. To that end, we introduce a new cost function: the average number of pseudo terminals per net in a multi way cut. Experiment result shows that our algorithm is very effective in terms of the number of chips used and the routability as compared to other methods.

Keywords

field programmable gate arrays; logic partitioning; multistage interconnection networks; optimisation; FPGA chips; architecture driven circuit partitioning; architecture driven partitioning algorithm; board routing; cost function; folded Clos network; multi FPGA emulation system; multi terminal nets; netlists; pseudo terminals; routability; Algorithm design and analysis; Computer architecture; Computer science; Cost function; Field programmable gate arrays; Integrated circuit interconnections; Partitioning algorithms; Permission; Pins; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on

Conference_Location

San Jose, CA, USA

Print_ISBN

1-58113-008-2

Type

conf

DOI

10.1109/ICCAD.1998.144299

Filename

742905