Title :
Performance enhancement in Asymmetric Gate Dielectric MOSFET
Author :
Havaldar, D.S. ; Katti, Guruprasad ; Jadeja, B.M. ; Rao, Ramesh ; DasGupta, Nandita ; Dasgupta, Avirup
Author_Institution :
Dept. of Electr. Eng., IIT Madras, Chennai
Abstract :
The asymmetric gate dielectric (AGD) MOSFET, where the equivalent dielectric thickness is higher at the source end than at the drain end, is studied with the help of simulations. A study of the properties of this device shows that, compared to the symmetric structure, the channel electric-field is larger at the source end resulting in higher carrier velocity and smaller at the drain end resulting in reduced short channel effects. The AGD devices show lesser drain induced barrier lowering and higher voltage gain compared to conventional devices, which should be useful for both digital and analog applications. The device structure has also been optimized for best performance.
Keywords :
MOSFET; dielectric devices; AGD devices; asymmetric gate dielectric MOSFET; performance enhancement; voltage gain; Acceleration; Charge carriers; Degradation; Dielectric materials; Doping; FETs; Hot carrier effects; MOSFET circuits; Nonuniform electric fields; Threshold voltage; Drain Induced Barrier Lowering (DIBL); Gate Dielectric; MOSFETs; voltage gain;
Conference_Titel :
Microelectronics, 2007. ICM 2007. Internatonal Conference on
Conference_Location :
Cairo
Print_ISBN :
978-1-4244-1846-6
Electronic_ISBN :
978-1-4244-1847-3
DOI :
10.1109/ICM.2007.4497742