Title :
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications
Author :
Nakatake, S. ; Sakanushi, K. ; Kajitani, Y. ; Kawakita, M.
Author_Institution :
Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
Abstract :
The BSG based packing of rectangles has been shown a breakthrough in problem size and generality, if routing is not involved. In order to include the routing, we define the channeled-BSG by associating the BSG-segs with channels. On the channeled-BSG, a new operation, flip, transforms an initial routing to another. Together with a formula that estimates the worst case width of channels for a given global routing, a solution space of simultaneous placement and routing is realized. It is proved that the space contains an optimal solution within the framework of the model. To search the space for a better solution, simulated annealing is implemented. Experiments to industrial data of analog LSIs showed a promising performance.
Keywords :
analogue integrated circuits; circuit layout CAD; integrated circuit layout; large scale integration; simulated annealing; BSG based packing; IC applications; analog LSIs; bounded sliceline grid; channeled-BSG; global routing; industrial data; optimal solution; rectangles; simulated annealing; simultaneous place/route; solution space; universal floorplan; worst case width; Analog circuits; Application specific integrated circuits; Data structures; Modeling; Permission; Polynomials; Routing; Simulated annealing; Systems engineering and theory;
Conference_Titel :
Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-008-2
DOI :
10.1109/ICCAD.1998.144301
