Title :
Iterative decoding of orthogonally concatenated code for fiber communications
Author :
Feixiang Yang ; Qingsheng Hu
Author_Institution :
Inst. of RF&OE-Ics, Southeast Univ., Nanjing, China
Abstract :
This paper presents a 10Gb/s concatenated BCH iterative decoder of super FEC. This iterative decoder consists of 3 row decoding modules and 2 column decoding modules which are cascaded together. Parallel decoding strategy is employed in the row decoder which reduces the total decoding latency from 1928 cycles to 578 cycles. Taking advantage of RAM blocks, the implementation of column decoding becomes easier compared to original structure. Other techniques like multiplexing and pipeline technology are adopted to improve the path delay and resource consumption. A 10Gb/s implementation is realized on FPGA device under the working frequency of 156.25 MHz.
Keywords :
BCH codes; concatenated codes; field programmable gate arrays; forward error correction; iterative decoding; optical fibre communication; FPGA device; Parallel decoding strategy; RAM blocks; bit rate 10 Gbit/s; concatenated BCH iterative decoder; fiber communications; iterative decoding; orthogonally concatenated code; super FEC; Bit error rate; Decoding; Delays; Forward error correction; Iterative decoding; Ports (Computers); Random access memory; BCH decoder; iterative decoding; multiplexing technique; super FEC;
Conference_Titel :
Instrumentation and Measurement, Sensor Network and Automation (IMSNA), 2013 2nd International Symposium on
Conference_Location :
Toronto, ON
DOI :
10.1109/IMSNA.2013.6743472