• DocumentCode
    332752
  • Title

    Tight integration of combinational verification methods

  • Author

    Burch, J.R. ; Singhal, V.

  • Author_Institution
    Cadence Berkeley Labs., CA, USA
  • fYear
    1998
  • fDate
    8-12 Nov. 1998
  • Firstpage
    570
  • Lastpage
    576
  • Abstract
    Combinational verification is an important piece of most equivalence checking tools. In the recent past, many combinational verification algorithms have appeared in the literature. Previous results show that these algorithms are able to exploit circuit similarity to successfully verify large designs. However, none of these strategies seems to work when the two input designs are not equivalent. We present our combinational verification algorithm, with evidence, that is designed to be robust for both the positive and the negative problem instances. We also show that a tight integration of different verification techniques, as opposed to a coarse integration of different algorithm, is more effective at solving hard instances.
  • Keywords
    equivalence classes; formal verification; logic CAD; circuit similarity; coarse integration; combinational verification methods; equivalence checking tools; hard instances; input designs; large designs; problem instances; tight integration; Automatic test pattern generation; Binary decision diagrams; Boolean functions; Circuit simulation; Computer bugs; Data structures; Robustness; Search engines; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA, USA
  • Print_ISBN
    1-58113-008-2
  • Type

    conf

  • DOI
    10.1109/ICCAD.1998.144325
  • Filename
    743060