Design and application of ATM-SDH multiplex/demultiplex ASIC

Author

Jun, Zhi ; Shaojun, Wei ; Hongyi, Chen

Author_Institution

Dept. of Microelectron., Tsinghua Univ., Beijing, China

fYear

1998

fDate

22-24 Oct 1998

Firstpage

27

Abstract

The combination of ARM and SDH is of great importance in the future high speed telecommunication network. In our work, we pointed out the need of the low speed ATM transmission through SDH, analyzed the system requirement planned an ASIC to implement the ATM-SDH multiplex/demultiplex system, designed the chip architecture, described the chip using VHDL coding, and implemented the chip by ALTERA FPGA. Several possible application configurations using the ASIC and the chip verification system are also introduced

Keywords

application specific integrated circuits; asynchronous transfer mode; demultiplexing equipment; integrated circuit design; multiplexing equipment; synchronous digital hierarchy; 19.44 MHz; 25.6 Mbit/s; 32 MHz; ALTERA FPGA; ATM-SDH multiplex/demultiplex ASIC; VHDL coding; chip architecture; chip verification system; high speed telecommunication network; low speed ATM transmission; system requirement; Application specific integrated circuits; Asynchronous transfer mode; Field programmable gate arrays; Packet switching; Process control; Road transportation; Signal processing; Switching circuits; Synchronous digital hierarchy; Telecommunication switching;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication Technology Proceedings, 1998. ICCT '98. 1998 International Conference on

Conference_Location

Beijing

Print_ISBN

7-80090-827-5

Type

conf

DOI

10.1109/ICCT.1998.743072

Filename

743072