VLSI Design for High-Speed Sparse Parity-Check Matrix Decoders

In this paper, the design of high-speed iterative decoders for sparse parity-check matrix (SPCM) codes such as LDPC, repeat-accumulate and turbo-like codes is addressed. The random nature of the underlying Tanner graph associated with these codes is problematic for a high-speed decoder implementation. This issue is addressed by designing structured SPCM codes tailored for low-complexity scalable decoders using the turbo-decoding message-passing (TDMP) algorithm. Analysis using EXIT charts shows that a better performance/complexity tradeoff is achieved when the number of decoding iterations is small which is attractive for high-speed applications. A scalable decoder architecture for structures SPCM codes employing the TDMP algorithm is presented