Designing for scan test of high performance embedded memories

Author

Vida-Torku, E. Kofi ; Joos, George

Author_Institution

Somerset Design Center, IBM Corp., Austin, TX, USA

fYear

1998

fDate

18-23 Oct 1998

Firstpage

101

Lastpage

108

Abstract

The addressing and clocking schemes in PowerPC^TM microprocessor embedded memories present modeling challenges. The ability of most scan based test tools to accurately generate test patterns for these embedded memories is limited. What is needed is aggressive Design for Test implementations that can help the test generation tools. In this paper we present our experiences in the design, modeling, and test of high performance embedded memories on the PowerPC microprocessors

Keywords

automatic test pattern generation; circuit CAD; design for testability; embedded systems; integrated memory circuits; logic CAD; logic simulation; memory architecture; microprocessor chips; random-access storage; Design for Test; PowerPC microprocessors; RAM model; addressing; clocking; high performance embedded memories; microprocessor embedded memories; modeling; scan test; test patterns; AC generators; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; DC generators; Logic arrays; Logic testing; Memory management; Microprocessors;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1998. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-5093-6

Type

conf

DOI

10.1109/TEST.1998.743142

Filename

743142