Title :
An algorithmic approach to optimizing fault coverage for BIST logic synthesis
Author :
Devadas, Srinivas ; Keutzer, Kurt
Author_Institution :
Lab. for Comput. Sci., MIT, Cambridge, MA, USA
Abstract :
Most approaches to the synthesis of built-in self-test (BIST) circuitry use a manual choose-and-evaluate approach, where a particular BIST generator is chosen and then evaluated by fault-simulating the design with the vectors that the chosen generator generates. We develop an algorithmic synthesis-during-test approach in this paper, wherein the tasks of synthesizing the BIST logic and directed test pattern generation (DTPG) are intertwined to maximize the resulting fault coverage. Our approach is applicable to a variety of BIST strategies including those that use linear- and nonlinear-feedback shift registers. We show how our method can be used to synthesize LFSR polynomials, LFSR seeds, LFSR weights, nonlinear feedback, or bit-fixing logic. Experimental data is presented
Keywords :
VLSI; built-in self test; circuit optimisation; design for testability; fault simulation; integrated circuit testing; integrated logic circuits; logic CAD; polynomials; random processes; shift registers; BIST logic synthesis; LFSR polynomials; LFSR seeds; LFSR weights; algorithmic synthesis-during-test; bit-fixing logic; built-in self test; directed test pattern generation; fault coverage; fault-simulation; linear-feedback shift registers; nonlinear feedback; Automatic testing; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Costs; Logic testing; Polynomials; Shift registers; Test pattern generators;
Conference_Titel :
Test Conference, 1998. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5093-6
DOI :
10.1109/TEST.1998.743149
