Title :
A Reconfigurable Fabric and Associated CAD Algorithms for Multirate LDPC Decoding
Author :
Mohiyuddin, Marghoob ; Prakash, Amit ; Wu, Xiang ; Aziz, Adnan
Author_Institution :
Dept. of EECS, California Univ., Berkeley, CA
fDate :
Oct. 28 2005-Nov. 1 2005
Abstract :
We present the design of a reconfigurable VLSI architecture suitable for multirate LDPC decoding. The basic decoder fabric is a square matrix of processing elements which communicate with each other through an interconnection network. The interconnection network consists of links and switches. The connectivity between processing elements is completely defined by scheduling the interconnection network; we describe a CAD algorithm for computing efficient schedules
Keywords :
VLSI; circuit CAD; decoding; matrix algebra; parity check codes; associated CAD algorithms; interconnection network; multirate LDPC decoding; reconfigurable VLSI architecture; reconfigurable fabric algorithms; square matrix; Computer networks; Decoding; Design automation; Fabrics; Multiprocessor interconnection networks; Parity check codes; Processor scheduling; Scheduling algorithm; Switches; Very large scale integration;
Conference_Titel :
Signals, Systems and Computers, 2005. Conference Record of the Thirty-Ninth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
1-4244-0131-3
DOI :
10.1109/ACSSC.2005.1599846
