Title :
A new approach to scan chain reordering using physical design information
Author :
Hirech, Mokhtar ; Beausang, James ; Gu, Xinli
Author_Institution :
Synopsys Inc., Mountain View, CA, USA
Abstract :
Scan chain reordering based on physical design information helps in reducing routing bottleneck and in minimizing design constraint violations. This paper proposes integrating this capability into synthesis-based design reoptimization. It describes the benefits of such an approach, the design synthesis context, presents new ordering concepts and concludes with results on real designs
Keywords :
VLSI; circuit optimisation; design for testability; integrated circuit layout; logic design; minimisation; network routing; design constraint; minimizing; physical design information; routing bottleneck; scan chain reordering; synthesis-based design reoptimization; Delay; Design for testability; Design optimization; Drives; Energy consumption; Routing; Signal design; Testing; Timing; Very large scale integration;
Conference_Titel :
Test Conference, 1998. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5093-6
DOI :
10.1109/TEST.1998.743173
