Applications of semiconductor test economics, and multisite testing to lower cost of test

Author

Evans, Andrew C.

Author_Institution

Teradyne Inc., Allentown, PA, USA

fYear

1999

fDate

1999

Firstpage

113

Lastpage

123

Abstract

This paper develops a Semiconductor Test Economic Model that can easily be applied to lowering overall cost of test and improving throughput. The “Model”, designed to take the complexity out of Test Economics, describes all the variables that make up cost per unit, and using managerial economic concepts, illustrates how they interact with each other, as well as the overall production goal of minimizing costs while maximizing throughput. This paper is written for Test Managers, Test Engineers, Product Engineers, and ATE Capital Equipment Buyers for the purpose of gaining insight analyzing test economics, in order to make better decisions on everyday Manufacturing issues related to: test time reduction, multisite testing, yield, handler index time, ATE utilization, and ATE purchasing

Keywords

automatic test equipment; cost-benefit analysis; integrated circuit economics; integrated circuit testing; integrated circuit yield; production testing; ATE purchasing; ATE utilization; capacity expansion; cost per unit; cost-benefit analysis; downtime cost; economic model; handler index time; improved throughput; lower cost of test; multisite testing; semiconductor test economics; test time reduction; yield; Cost benefit analysis; Design engineering; Economic indicators; Engineering management; Investments; Production; Pulp manufacturing; Semiconductor device manufacture; Semiconductor device testing; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1999. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-5753-1

Type

conf

DOI

10.1109/TEST.1999.805620

Filename

805620