DocumentCode
3328636
Title
The test and debug features of the AMD-K7TM microprocessor
Author
Wood, Timothy J.
Author_Institution
Texas Microprocessor Div., Adv. Micro Devices Inc., Austin, TX, USA
fYear
1999
fDate
1999
Firstpage
130
Lastpage
136
Abstract
The time-to-volume and production manufacturing requirements drove the test methodology chosen for the seventh generation AMD x86 compatible processor. The use of embedded hardware to meet the test objectives includes considerations for debug support from wafer level test through systems level test. The use of ATPG to generate high stuck-at fault coverage tests was central to top-level design considerations of the AMD-K7TM processor. Partitioning choices were also made to ensure ATPG produced tests could be enhanced with additional test sets targeting other fault models. This paper describes the design-for-test and design-for-debug features of the AMD-K7TM microprocessor
Keywords
automatic test pattern generation; boundary scan testing; built-in self test; computer debugging; design for testability; embedded systems; fault simulation; integrated circuit testing; logic testing; microprocessor chips; pipeline processing; AMD-K7 microprocessor; ATPG; BIST; JTAG interface; debug support; design-for-debug features; design-for-test features; embedded hardware; fault models; high stuck-at fault coverage; internal scan pattern generation; partitioning choices; pipeline processor; superscalar microprocessor; systems level test; test methodology; top-level design; wafer level test; Automatic test pattern generation; Built-in self-test; CMOS technology; Clocks; Design for testability; Job shop scheduling; Logic testing; Microprocessors; Processor scheduling; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1999. Proceedings. International
Conference_Location
Atlantic City, NJ
ISSN
1089-3539
Print_ISBN
0-7803-5753-1
Type
conf
DOI
10.1109/TEST.1999.805622
Filename
805622
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