Compact hardware implementation of SHA-3 finalist blake on FPGA

NIST announced a public competition on Nov. 2, 2007 to develop a new cryptographic hash algorithm. Blake is one of the candidate among five finalist selected in round three of this competition. One of the major evaluation criteria of the candidate algorithm is efficient hardware implementation. In this paper compact area-efficient design of Blake-256 algorithm is implemented on FPGA. Horizontal Folding and pipelining technique is used in which two Half-G functions are used to execute overall round function. Distributed Block Memory is used for storing permutation table values. Full autonomous design is implemented on Virtex 5 LX-50T FPGA. The Post Place and Route results shows area utilization of 415 Slices with the maximum achieved frequency of 196 MHz and throughput of the design is calculated as 717 Mbps. Throughput per Area of our design is 1.72 which shows the significant improvement in results from all previous reported work.