Title :
DFT advances in the Motorola´s MPC7400, a PowerPCTM G4 microprocessor
Author :
Pyron, Carol ; Alexander, Mike ; Golab, James ; Joos, George ; Long, Bruce ; Molyneaux, Robert ; Raina, Rajesh ; Tendolkar, Nandu
Author_Institution :
Somerset Design Centre, Austin, TX, USA
Abstract :
Several advances have been made in the design for testability of the MPC7400, the first fourth generation PowerPC microprocessor. The memory array built-in self-test algorithms now support detecting write-recovery defects and more comprehensive diagnostics. Delay defects can be tested with scan patterns with the phased locked loop providing the at-speed launch-capture events. Several methodology and modeling improvements increased LSSD stuck-at fault test coverage. Design for manufacturability enhancements provide better tracking of initial silicon and fuse-based memory repair capabilities for improved yield and time-to-market
Keywords :
automatic test pattern generation; built-in self test; design for manufacture; design for testability; fault simulation; integrated circuit testing; logic testing; microprocessor chips; parallel architectures; ATPG; DFT advances; Motorola MPC7400; PLL; at-speed launch-capture events; delay defects; design for manufacturability; fault testing; fourth generation PowerPC microprocessor; fuse-based memory repair; improved time-to-market; improved yield; memory array BIST algorithms; modeling improvements; redundancy repair; scan patterns; silicon repair; stuck-at fault test coverage; superscalar μP; write-recovery defects; CMOS technology; Circuit faults; Circuit testing; Clocks; Delay; Design for testability; Latches; Logic testing; Microprocessors; Silicon;
Conference_Titel :
Test Conference, 1999. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5753-1
DOI :
10.1109/TEST.1999.805623
