DocumentCode :
332868
Title :
Towards an automatic diagnosis for high-level design validation
Author :
Khalil, Maisaa ; Le Traon, Yves ; Robach, Chantal
Author_Institution :
LCIS-INPG, Valence, France
fYear :
1998
fDate :
18-23 Oct 1998
Firstpage :
1010
Lastpage :
1018
Abstract :
In this paper, we focus on high level design diagnosis. A novel diagnosis strategy is presented which allows faults to be automatically located. Given a system under test, this method effectively restricts the suspected parts in order to correct the detected faults
Keywords :
automatic test pattern generation; fault simulation; flow graphs; high level synthesis; ATPGs; automatic diagnosis; detected faults; diagnosis strategy; fault simulation; high-level design validation; system under test; Automatic control; Automatic testing; Circuit faults; Circuit testing; Control systems; Fault detection; Fault diagnosis; Fault location; Hardware; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1998. Proceedings., International
Conference_Location :
Washington, DC
ISSN :
1089-3539
Print_ISBN :
0-7803-5093-6
Type :
conf
DOI :
10.1109/TEST.1998.743298
Filename :
743298
Link To Document :
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