Breaking the complexity spiral in board test

The task of developing comprehensive programs to test today´s ever-more-complex printed-circuit boards ranges from the daunting to the impossible, and it gets more difficult all the time. Short-run application-specific ICs replace scores of high-volume “jelly-bean” parts. The number of patterns necessary to execute an exhaustive test increases geometrically with the number of gates. Gate to access-node ratios at both device and board levels continue to skyrocket, while test development tools improve more modestly. As a result, test operations increasingly represent the primary impediment to delivering good products on time. This paper examines breaking this spiral by pushing some traditional board-test responsibilities back to the device level. Issues include design-for-testability, boundary-scan, built-in self-test, and test-program generation