On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on Chip

This paper introduces a state-of-the-art design of a high speed sigma delta digital to analog converter (DAC), which can be integrated into a system-on-a-chip (SOC) for different communication transceivers. The operation speed in the digital circuit is very important for accomplishing the performance which can satisfy different communication protocol specifications. This paper therefore addresses this problem by using a parallel structure for radio frequency modulation at system level and by using redundancy coding for speed improvement at register transfer level. Due to the flexibility of the sigma delta structure, the designs can trade off between bandwidth and signal-to-noise ratio (SNR) to adapt to different digital communication protocol specifications. A 4th order structure can e.g. achieve 6.5 MHz single-side bandwidth (SBW) with 99 dB SNR at base band; or it can achieve 26 MHz double-side bandwidth with 73 dB SNR. Moreover, if latches are used, the sampling frequency can reach 1.4 GHz in a 5th order 2bit structure implemented in a 0.13 mum ASIC, which can achieve 29 MHZ SBW with 81 dB SNR. These implementations occupy very little area as demonstrated in the data obtained from synthesis in a 0.13 mum CMOS standard cell library. These sigma delta structures therefore can be integrated in a SOC for different digital communication transceivers effectively.