W-CDMA hardware-related issues

Author

Ishikawa, Toshihiro ; Suzuki, Hidetoshi ; Minamida, Noriaki ; Yamanaka, Ryutaro ; Okamoto, Minoru ; Kabuo, Hideyuki ; Taki, Hideshi

Author_Institution

Telecomm. Res. Lab., Matsushita Commun. Ind. Co. Ltd., Yokosuka, Japan

fYear

1998

fDate

22-24 Oct 1998

Firstpage

505

Abstract

Overviews W-CDMA hardware-related issues and shows requirements for key devices of the W-CDMA and a solution for DSP, We propose a DSP architecture suited for W-CDMA. The main features of this architecture are: 1) highly efficient Viterbi error correction operation, 2) ability to perform a multiply-accumulate operation and store the result to data memory in a single cycle when used in conjunction with a repeat instruction, 3) support for the double precision (40 bit) operations and data, 4) ability to perform a DMA to/from a fixed portion of internal memory without interrupting the processor. These features allow implementation of a W-CDMA voice channel less than 100 MIPS

Keywords

CMOS digital integrated circuits; broadband networks; cellular radio; code division multiple access; digital radio; digital signal processing chips; error correction; radio equipment; 0.35 micron; 100 MIPS; 40 bit; CMOS IC; DMA; DSP architecture; MAC operation; Viterbi error correction operation; W-CDMA hardware-related issues; data memory; double precision operations; internal memory; key devices; multiply-accumulate operation; repeat instruction; voice channel; Codecs; Digital signal processing; Error correction; High power amplifiers; Low-noise amplifiers; Multiaccess communication; Radio frequency; Radiofrequency amplifiers; Video signal processing; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication Technology Proceedings, 1998. ICCT '98. 1998 International Conference on

Conference_Location

Beijing

Print_ISBN

7-80090-827-5

Type

conf

DOI

10.1109/ICCT.1998.743334

Filename

743334