Title :
Accurate path delay fault coverage is feasible
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Abstract :
We examine the problem of determining the exact number of path delay faults that a given set of p pairs of patterns detects in a combinational circuit consisting of I lines. Several fault coverage pessimistic heuristics and exact algorithms with worst case exponential behavior have been recently presented with trade-offs between the quality of fault coverage and the time performance. None of the existing approaches has provably good performance. This paper presents the first polynomial time algorithms that calculate the path delay fault coverage exactly. Experimental results on the ISCAS´85 benchmarks demonstrate the effectiveness of the presented approaches
Keywords :
automatic test pattern generation; circuit complexity; combinational circuits; delay estimation; fault diagnosis; fault simulation; integrated circuit testing; logic testing; polynomial approximation; timing; ATPG; ISCAS´85 benchmarks; accurate path delay fault coverage; combinational circuit; fault coverage pessimistic heuristics; fault grading problem; path delay faults; polynomial time algorithms; time complexity; worst case exponential behavior; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Delay effects; Electrical fault detection; Fault detection; Heuristic algorithms; Polynomials; Sequential circuits;
Conference_Titel :
Test Conference, 1999. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5753-1
DOI :
10.1109/TEST.1999.805631