DocumentCode
3329048
Title
A new LSI design for the achievement of robust system
Author
Hatakawa, Yasuyuki ; Miyanaga, Yoshikazu
Author_Institution
Graduate Sch. of Inf. Sci. & Technol., Hokkaido Univ., Sapporo, Japan
fYear
2004
fDate
18-19 Nov. 2004
Firstpage
746
Lastpage
749
Abstract
The report presents a robust architecture for VLSIs. The proposed architecture achieves robustness only by using a small overhead, since it reconfigures the circuit to eliminate malfunctions. In addition, the report introduces a Viterbi decoder designed with the robust architecture and evaluates its performance by computer simulation.
Keywords
VLSI; Viterbi decoding; circuit stability; integrated circuit design; large scale integration; parallel processing; VLSI; Viterbi decoder; parallel processing; robust LSI design; robust architecture; robust system; Computer architecture; Decoding; Equations; Large scale integration; Parallel architectures; Pipelines; Robustness; Switches; Switching circuits; Viterbi algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Signal Processing and Communication Systems, 2004. ISPACS 2004. Proceedings of 2004 International Symposium on
Print_ISBN
0-7803-8639-6
Type
conf
DOI
10.1109/ISPACS.2004.1439158
Filename
1439158
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