Practical scan test generation and application for embedded FIFOs

Author

Rearick, Jeff

Author_Institution

Hewlett-Packard Co., Fort Collins, CO, USA

fYear

1999

fDate

1999

Firstpage

294

Lastpage

300

Abstract

This paper describes a method for testing non-scanned embedded latch-based FIFOs on an otherwise full-scan chip by using the scan registers that surround the FIFO and sharing the test application time with the other ASIC scan tests. The technique of excising the FIFOs from the ASIC to allow separate and effective test generation for each is explained, as is the process used to merge the two tests back together for efficient test application. Results are presented for three example ASICs which indicate that the method is both efficient and thorough

Keywords

application specific integrated circuits; automatic test pattern generation; boundary scan testing; design for testability; embedded systems; fault simulation; integrated circuit testing; logic simulation; logic testing; memory architecture; ASIC scan tests; ATPG flow; DFT; FIFO memory design; VLSI chips; embedded latch-based FIFOs; fault simulation; full-scan chip; logic simulation; scan registers; scan test generation; test application; test application time; Application specific integrated circuits; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Design for testability; Flip-flops; Integrated circuit testing; Logic testing; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1999. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-5753-1

Type

conf

DOI

10.1109/TEST.1999.805643

Filename

805643