An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264

Author

Bhavsar, Dilip K.

Author_Institution

Alpha Dev. Group, Compaq Comput. Corp., Shrewsbury, MA, USA

fYear

1999

fDate

1999

Firstpage

311

Lastpage

318

Abstract

An innovative self-test and self-repair technique supports built-in self-test and built-in self-repair of large embedded RAM arrays with spare rows and columns. The technique generates and analyzes the required failure bitmap information on the fly during self-test and then automatically repairs and verifies the repaired RAM arrays

Keywords

automatic test pattern generation; built-in self test; cellular arrays; design for testability; embedded systems; finite state machines; integrated circuit testing; logic testing; microprocessor chips; reduced instruction set computing; Alpha 21264 implementation; built-in self-repair; built-in self-test; large embedded RAM arrays; required failure bitmap information; row-column self-repair; self-repair logic; spare allocation problem; spare rows and columns; superscalar RISC microprocessor; test algorithm engine; Built-in self-test; Driver circuits; Embedded computing; Failure analysis; Information analysis; Logic testing; Microprocessors; Read-write memory; Reduced instruction set computing; Semiconductor device manufacture;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1999. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-5753-1

Type

conf

DOI

10.1109/TEST.1999.805645

Filename

805645