Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs

We propose a concurrent error detection (CED) scheme for a network of combinational logic blocks implemented with memory embedded in FPGAs. The proposed scheme is proven to detect - without latency - any permanent or transient fault associated with a single input or output of any component of the network. The experimental results show that the overhead for the presented CED technique is low (23.9% for the examined network), especially when compared with solutions intended for gate-based designs (55% or 81%, depending on the technique, for the same network).