A supply and process-insensitive 12-bit DPWM for digital DC-DC converters

This paper presents the design of a supply and process-insensitive 12-bit digital pulse width modulator (DPWM) for digital DC-DC converters. The DPWM is realized by a counter and a ring oscillator-multiplexer segmented tapped delay line. The ring oscillator of the tapped delay line is made insensitive to supply and process variation by biasing the differential delay cells with a supply-insensitive replica bias circuit. Simulation results show that the variation of the switching frequency of the DPWM at 1.03 MHz is 0.4% for supply voltage variation between 1.5 V and 2.5 V and 0.95% over the temperature range from -40degC to 90degC. Monte-Carlo simulation was also performed to account for the effect of mismatch between the transistors of the ring oscillator. The worst case delay of the delay cells is 0.87% for plusmn5% (3-sigma) mismatch.