Checking sequence generation for asynchronous sequential elements

An algorithm for generating checking sequences for asynchronous finite state machines is proposed. A checking sequence distinguishes a finite state machine (FSM) from all other FSMs with the same inputs and outputs, and with the same or fewer number of states. This algorithm is applied to normal fundamental mode asynchronous finite state machines (AFSM). The derived checking sequences can be used either as a test sets that detect all logic faults or to verify that the circuit design as a correct implementation of the AFSM. The resulting test is guaranteed to detect all logic faults occurring in the machine even if the defect causes a limited number of additional states