Title :
A DLL-regulated SIMO power converter for DVS-enabled power-aware VLSI systems
Author :
Bondade, Rajdeep ; Ma, Dongsheng
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Arizona, Tucson, AZ, USA
Abstract :
A delay-locked loop (DLL) regulated single-inductor multiple-output (SIMO) power converter is presented. It takes advantage of the fast phase locking property of a DLL to identify the SIMO converter´s regulation errors between the output voltages and their corresponding references. In response to these errors, an adaptive peak current modulation technique is proposed to adjust the instantaneous duty ratios, and thus minimize the regulation errors in the converter. The DLL acquires locking within 350 ns, allowing it to respond to load dynamics promptly, which is very desirable for DVS-enabled power-efficient VLSI systems. The system was designed and simulated in IBM 130-nm CMOS process. Fully transistor-based HSPICE simulations show that, with a 1.8 V nominal input supply, the converter precisely regulates two independent output voltages at 0.9 V and 1.5 V, respectively. It achieves the maximum efficiency of 87.2% at a total power of 104.8 mW and a switching frequency of 500 kHz.
Keywords :
CMOS digital integrated circuits; SPICE; VLSI; delay lock loops; power convertors; power inductors; voltage regulators; CMOS process; DLL; DVS-enabled power-aware VLSI systems; HSPICE simulations; delay-locked loop; frequency 500 kHz; instantaneous duty ratios; power 104.8 mW; single-inductor multiple-output power converter; size 130 nm; voltage 0.9 V; voltage 1.5 V; voltage 1.8 V; DC-DC power converters; Delay; Error correction; Inductors; Integrated circuit noise; Network-on-a-chip; Power dissipation; Pulse width modulation; Very large scale integration; Voltage control;
Conference_Titel :
Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on
Conference_Location :
Cancun
Print_ISBN :
978-1-4244-4479-3
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2009.5235926