An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty

The design of clock distribution networks in synchronous digital systems presents great challenges. In other words, controlling the clock signal delay in the presence of process parameter variations is a major problem in the design of high-speed synchronous circuits. In this paper, an efficient algorithm is presented to improve the tolerance of a clock distribution network against process variation. This algorithm generates a non-tree clock network for reducing uncertainty of the clock signal delay introduced by process variation. The non-tree clock network is generated by inserting cross links in appropriate points taking critical paths into account. To evaluate the effectiveness of the proposed algorithm several HSPICE-based Monte Carlo simulations were done. Experimental results show that the proposed approach can lead to a significant reduction in the deviation of signal propagation delay of critical paths and the skew variability without considerable increase in the total wirelength.