Defect-based delay testing of resistive vias-contacts a critical evaluation

Author

Baker, Keith ; Gronthoud, Guido ; Lousberg, Maurice ; Schanstra, Ivo ; Hawkins, Charles

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

fYear

1999

fDate

1999

Firstpage

467

Lastpage

476

Abstract

This defect-based study analyzes statistical signal delay properties and delay fault test pattern constraints in the CMOS deep submicron environment. Delay fault testing has uncertainty, or noise, in its attempt to detect defects that slow a signal. CMOS resistive vias and contacts were used as a delay defect target. Data were taken from a scan-based test chip (Veqtor) on the Philips 0.25 μm technology. Methods to improve delay fault defect detection are given

Keywords

CMOS logic circuits; delays; failure analysis; fault diagnosis; integrated circuit testing; logic testing; statistical analysis; 0.25 mum; CMOS; MOS resistive vias; Philips; Veqtor; critical evaluation; defect-based analysis; delay defect target; delay fault defect detection; delay fault test pattern; delay testing; noise; resistive vias-contacts; scan-based test chip; signal delay properties; statistical analysis; Circuit faults; Circuit testing; Clocks; Delay; Fault detection; Integrated circuit modeling; Integrated circuit testing; Logic testing; System testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1999. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-5753-1

Type

conf

DOI

10.1109/TEST.1999.805769

Filename

805769