Charge signal processors in sparse readout CMOS MAPS and hybrid pixel sensors for the SuperB Layer0

This work will discuss the design of analog circuits for processing the signals from deep N-well monolithic CMOS sensors and from high resistivity substrate pixel detectors. Several options for the design of the SuperB Layer0 are being studied. Hybrid pixel detectors are nowadays a robust and mature technology for the innermost vertex detector layer, but they require a relatively large material budget which can make them marginal for the foreseen application. CMOS MAPS technology has the potential for providing very thin detectors since the sensor and the readout electronics are integrated in the same substrate. Recently, a very promising approach to MAPS based on the use of a vertically integrated CMOS technology has also been considered. Various solutions complying with different S/N ratio and detector capacitance constraints have been studied and implemented in a planar 130 nm CMOS technology and in a 130 nm CMOS technology with vertical integration capabilities. This paper intends to describe and compare the features of the different options by means of simulations and experimental results.