The value of tester accuracy

Author

Dalal, Wajih ; Miao, Song

Author_Institution

Schlumberger Technol., San Jose, CA, USA

fYear

1999

fDate

1999

Firstpage

518

Lastpage

523

Abstract

This article outlines the importance of the tester edge placement accuracy (EPA) for device testing. In particular we quantify the value of that accuracy to the Rambus manufacturer in terms of yield loss and escapes (in DPM). A simulation is presented that models the tester accuracy, the device edge distribution and their interaction at the current Rambus speed of 800 Mbps. The same model can be applied for microprocessors or other parts that operate near the limits of ATE performance. With the estimated RDRAM yields and selling prices, the model shows a value of over a ε for every 1ps of enhanced accuracy

Keywords

DRAM chips; automatic test equipment; digital simulation; integrated circuit economics; integrated circuit testing; integrated circuit yield; measurement errors; microprocessor chips; production testing; timing; 800 Mbit/s; ATE performance; DPM; RDRAM yields; Rambus manufacturer; Rambus speed; device edge distribution; device testing; edge placement accuracy; escapes; microprocessors; model; prices; simulation; tester accuracy; yield loss; Accuracy; Automatic testing; Loss measurement; Manufacturing; Microprocessors; Probability; Process design; Random access memory; Timing; Uncertainty;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1999. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-5753-1

Type

conf

DOI

10.1109/TEST.1999.805775

Filename

805775