A low-jitter digital-to-frequency converter based frequency multiplier with large N

In video and graphic digitizing applications, synthesizing a high-frequency clock from a very low-frequency is often needed. In these applications, the multiplication factor N could be very large (Nges1000). It is difficult for a conventional phase-locked-loop (PLL) to handle such a large N, due to the large amount of jitter at the low-frequency input. This paper presents a new method of frequency multiplication that is able to handle such a large N while maintaining low jitter in the synthesized clock. Moreover, a random dithering technique is introduced in this architecture to reduce spurious noise and shape clock spectrum for lower electromagnetic interference (EMI).