BIST for phase-locked loops in digital applications

Author

Sunter, Stephen ; Roy, Aubin

Author_Institution

Logic Vision Inc., Ottawa, Ont., Canada

fYear

1999

fDate

1999

Firstpage

532

Lastpage

540

Abstract

Phase-locked loops (PLLs) are an essential building block of most digital and mixed-signal ICs. This paper describes a built-in self-test (BIST) circuit that tests the key analog parameters of PLLs, using only logic gates that can be synthesized from a hardware description language (HDL). The parameters tested include lock range, lock time, RMS jitter, and loop gain (from which the natural frequency is calculated). Experimental waveforms and results are shown for a 200 MHz PLL which uses a phase-frequency detector. Test time is typically 10 ms, much faster than for conventional testing

Keywords

automatic testing; built-in self test; digital phase locked loops; gain measurement; hardware description languages; integrated circuit testing; jitter; time measurement; 10 ms; 20 kHz to 200 MHz; 200 MHz; BIST; HDL; PLL; RMS jitter; built-in self-test; digital IC; digital applications; hardware description language; lock range; logic gates; loop gain; mixed-signal IC; natural frequency; phase-frequency detector; phase-locked loops; test time; Automatic testing; Built-in self-test; Circuit synthesis; Circuit testing; Hardware design languages; Logic circuits; Logic gates; Logic testing; Phase frequency detector; Phase locked loops;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1999. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-5753-1

Type

conf

DOI

10.1109/TEST.1999.805777

Filename

805777