The implementation and design methodology of a quad-core version Godson-3 microprocessor

Author

Fan, Baoxia ; Yang, Liang ; Gao, Zhuo ; Zhang, Feng ; Wang, Ru

Author_Institution

Key Lab. of Comput. Syst. & Archit., CAS, Beijing, China

fYear

2009

fDate

2-5 Aug. 2009

Firstpage

1167

Lastpage

1170

Abstract

Godson-3A is a quad-core version of Godson-3 series which is a 174 mm², 425 million transistors chip fabricated using 65 nm CMOS LP/GP process technology. It can be running at 1 GHz with less than 15 W power consumption. Large scale, high frequency, low power and tight time schedule make great challenges in the chip design. To overcome these challenges, a design methodology based on ASIC combining with semi-custom (manual placement and routing using standard cells) and full-custom is adopted. This paper describes the implementation of Godson-3A microprocessor and the methodology used in the chip design.

Keywords

CMOS integrated circuits; application specific integrated circuits; microprocessor chips; power consumption; transistors; ASIC; CMOS LP-GP process technology; chip design; design methodology; power consumption; quadcore version Godson-3 microprocessor; transistors chip; Application specific integrated circuits; CMOS process; CMOS technology; Chip scale packaging; Design methodology; Energy consumption; Frequency; Large-scale systems; Microprocessors; Processor scheduling;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on

Conference_Location

Cancun

ISSN

1548-3746

Print_ISBN

978-1-4244-4479-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2009.5235942

Filename

5235942