Robust and high performance subthreshold standard cell design

Digital subthreshold circuits are gaining importance because of their ability to serve as an ideal low power solution. In this paper, a methodology to design a performance enhanced subthreshold standard cell library robust to process variations is discussed. Several approaches to design a performance enhanced cell library are discussed and an optimal design choice is made with energy-delay product as a metric. Significant performance improvements of 2X, 8X and 1.5X are achieved for inverter, AND, and OR cells respectively over regular cell library. The variation in delay for the proposed standard cell library with respect to four process corners is studied. A significant reduction of about 75.6% in delay variation across worst case process corners was observed when a normal inverter and inverter from the high performance cell library were simulated.