SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level

Author

Yadavalli, Sitaram ; Reddy, Sudhakar M.

Author_Institution

Test Technol., Intel Corp., Santa Clara, CA, USA

fYear

1999

fDate

1999

Firstpage

606

Lastpage

615

Abstract

This paper presents a technique and tool (SymSim) for symbolic fault-simulation of data-paths specified at the Register-Transfer Level (RTL) constrained by specific control sequences. SymSim achieves this using a symbolic value system suitable for RTL simulation. It also computes and maintains input dependency information at each node in the design using a novel artifact called Dependency Set which at any time-frame contains all primary input symbols that effect the current value on that node. Symbolic fault-simulation can be used along with a symbolic test-generator to detect multiple faults with a single test to reduce test length and and generation time

Keywords

VLSI; automatic testing; binary sequences; combinational circuits; fault simulation; integrated circuit testing; logic CAD; logic testing; Dependency Set; RTL simulation; Register-Transfer level; SymSim; VLSI; control sequences; data-flow data-path design; input dependency; multistage combinational test schedule; primary input symbols; symbolic fault simulation; symbolic test-generator; time-frame; Circuit faults; Circuit testing; Computational modeling; Digital signal processing; Electrical fault detection; Fault detection; Hardware design languages; Logic testing; Multiplexing; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1999. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-5753-1

Type

conf

DOI

10.1109/TEST.1999.805785

Filename

805785