ATM cell scheduling with queue length-based priority scheme

The asynchronous transfer mode (ATM) is the choice of transport mode for B-ISDN. In this paper, we propose a window-based ATM cell scheduling scheme using a neural network to achieve higher throughput for nonblocking ATM switches. In a nonblocking switch with input queues, significant loss of throughput can occur due to head-of-line blocking when FIFO queueing is employed. To resolve this problem, we propose an optimal input bypass queueing method which maximizes switch throughput. We also employ a queue length based priority scheme to reduce cell delay variations and cell loss probabilities. With the employed priority scheme, the variance of delay is also significantly reduced under nonuniform traffic, resulting in lower cell loss rates at a given buffer size. Due to higher switch throughput achieved with our cell scheduling, the cell loss probabilities and the buffer sizes necessary to guarantee a given cell loss rate become even smaller than those with output queueing that has been known to provide better performance than input queueing