• DocumentCode
    3330804
  • Title

    Embedded Diagnostic Logic Test Exploiting Regularity

  • Author

    Vierhaus, H.T. ; Kothe, R.

  • Author_Institution
    Comput. Eng. Group, Brandenburg Univ. of Technol. Cottbus, Brandenburg
  • fYear
    2008
  • fDate
    3-5 Sept. 2008
  • Firstpage
    873
  • Lastpage
    879
  • Abstract
    Fault diagnosis has recently become an important issue in IC production test because of the need to enforce high manufacturing yield. Furthermore, fault diagnosis is a pre-condition for any technology of built-in self repair that may be used in the field of application where long-time dependable systems are necessary. An "embedded" diagnostic self test has to get along with a minimum of memory space and computing power, since it may have to make a system working during a system start-up phase. Using inherent regularity on logic de-signs can simplify diagnostic tests considerably by reducing the amount of reference data significantly.
  • Keywords
    fault diagnosis; integrated circuit testing; logic testing; built-in self repair; embedded diagnostic logic test; embedded diagnostic self test; fault diagnosis; high manufacturing yields; logic designs; long-time dependable systems; Automatic testing; Circuit testing; Clocks; Compaction; Flip-flops; Logic design; Logic gates; Logic testing; Sequential analysis; Space technology; Built-in Self-repair; Embedded Diagnosis; Fault diagnosis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital System Design Architectures, Methods and Tools, 2008. DSD '08. 11th EUROMICRO Conference on
  • Conference_Location
    Parma
  • Print_ISBN
    978-0-7695-3277-6
  • Type

    conf

  • DOI
    10.1109/DSD.2008.124
  • Filename
    4669328