Test support processors for enhanced testability of high performance circuits

A solution for testing fast-switching bidirectional signal lines using an array of technology-specific transceivers has been described previously (1998). This method uses an active component located between the device-under-test (DUT) and the automated test equipment (ATE) to reduce electrical interconnect delays to less than 150 ps. In this paper, the transceiver array concept is extended to include higher-level test processes such as real-time algorithmic pattern generation (APG), multi-gigahertz signal multiplexing, and others. The active test component is therefore called a “Test Support Processor” (TSP). It greatly reduces the functionality and performance capability required of the ATE, while maintaining signal integrity, and improving overall test quality. In its minimum configuration, the TSP provides an array of technology-specific transceivers very close to the DUT. This reduces transmission line effects, allowing for at-speed test of fast I/O switching characteristics. This technique may lead to lower-cost. The TSP is specifically intended to complement and support existing DFT and BIST structures within the DUT. The use of the TSP provides an additional degree of freedom for partitioning the test problem, and may result in a significant paradigm shift for future ATE architectures. This paper describes variations of the TSP concept, its potential applications, and economic impact. Three variations are illustrated through prototype demonstrations, including: (A) a 2.67 Gbps test pattern source, (B) a transceiver array for testing a high speed 4 Mbit SRAM, and (C) a reconfigurable real-time APG for memory testing, implemented using a field-programmable gate array (FPGA)