• DocumentCode
    3330925
  • Title

    Design-for-test methodology for Motorola PowerPCTM microprocessors

  • Author

    Abadir, Magdy ; Raina, Rajesh

  • Author_Institution
    Motorola Inc., Austin, TX, USA
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    810
  • Lastpage
    819
  • Abstract
    Testing of modern microprocessor designs remains a challenging problem. At Motorola´s Somerset Design Center, we rely heavily on Design-For-Test (DFT) to address these challenges. To date our efforts have been very successful. This paper reviews our DFT methodology and how the DFT group is dealing with the new challenges that are facing PowerPCTM microprocessor designs
  • Keywords
    design for testability; integrated circuit testing; logic testing; microprocessor chips; DFT; Motorola PowerPCmicroprocessors; Motorola Somerset Design Center; microprocessor design; Bandwidth; Costs; Design for testability; Digital signal processors; Distributed computing; Frequency; Hardware; Internet; Microprocessors; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1999. Proceedings. International
  • Conference_Location
    Atlantic City, NJ
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-5753-1
  • Type

    conf

  • DOI
    10.1109/TEST.1999.805812
  • Filename
    805812